True that they are clock edges but I don't know time period of A. if A is high for 4 clock periods, then C must be high for 2 clock periods (rise one clock period after A, and fall one clock period before A). And if A is high for 7 clock periods then C is high for 5.
The delaying A makes sense...
I wasn't told about anything about that. Just a few waveforms were drawn by hand and then I was asked if I can get them as output. I suggested using And gate and buffers for the first waveform where only the leading edge has a delay. For the second waveform, i tried but eventually said it...
Yeah even I was like mostly sure that it can't be done. We can't anticipate the falling edge of the input without any previous information.
Maybe it can be done if like we have history. Like one clock cycle of input passes and from second clock cycle, we want the output to act in a particular...
Vertical lines represent clock edges. The professor said you can use whatever circuit you feel like. The professor was convinced when I said use buffer gates and And gate for B waveform, but then he asked can C ever be done.
A is given waveform, we have to use circuits to get B and C waveform. For B we can use an And Gate with 2 inputs, X and Y. X is buffered (to get some delay) and is fed to Y input of And Gate. So we'll get waveform B.
But I don't know how to get C waveform. The question is that even if I extend...
Yes. If OR-1 is high or low it doesn't matter what the output of And-2 is. But my confusion is suppose in transition state. Like if the output is going from high to low. Suppose Or-1 and And-2 outputs are high. And now if due to logic change in A input, Or-1 goes low, so it will take some time...
The output of And-2 depends on C as well, but it doesn't matter when final output is 1 because it's an OR-gate at the end. if output of Or-1 is high, then the output will always be high irrespective of and-2 gate output.
What's bothering me is that what if there is an initial condition. Like initially the output is high and also output of And-2 is high. Now if A goes to 0, and B goes to 1, then the final output will have to wait for And-2 to become low. So we cannot remove And-2 from the longest path in this case.
I'm not sure how will this oscillator work. Assume A is low, so B will be high and the capacitor will charge through B-C- 2Mohm.
Now even D has gone high, so A will be high and B will be low and C will discharge. I'm not sure how the voltage divider rule across RC will take into effect.
I found...
We haven't been given any test bench. Inactive path would be like:
For Gate: OR-2, if the output of OR-1 is high, then the lower input for Gate OR-2 makes no difference. So we can say it's inactive. Like for calculation of delay purpose in case the output is logic-1.
First for logic-1 at output: So I get that for Logic 1, the OR-2 Gate must have one input has logic-1.
Case1: Upper OR-Input is 1 of second OR Gate. So the longest path is Inv-1, Or-1, Or-2. Delay is 9ns.
Case2: For lower input to be 1, the 'And-2' output has to be 1, and for that Or-1 output...
I haven't come across this circuit. We've come across questions like: advantage of cmos over transmission gates, draw cmos for nand gate and nor gate.
given a logical expression: AB + (C (A + B) ). Draw its CMOS configuration.
My resume has a verilog project. I put more focus on that subject...
For logic table A = not(C) * not(F) not means inverted. * means 'and' gate
B = not(A)
C = not(F)
Output = not(C)
What do 'gates be neither high nor low' mean?
If the FET has very high resistance (both FET in series), the resistance of the path becomes very high and resistance will oppose any current. Unless the current is being forced to flow through it. In that case the voltage would be very high.
But even then the Vss will split as per the voltage...
Is it mandatory to use Thevenin's equivalent? You can solve the question without it as well. You've given the current, so that will either give a constant Vo or Vo in the form of an equation.
Well if the FET had very high resistance, then I guess there wouldn't be any drop across it. Leakage current would be zero as it's like an open circuit. So voltage would be 5 V
I made a table using excel as:
D is output. Like this I get Output frequency is same as input frequency. But I'm not sure if this is correct.
PS: I'm aware I'm posting many questions, but I got interview exams coming up in August. Companies are gonna come to university for recruitment and thus...
I use the voltage divider rule as output voltage = Voltage across R1 = 5 * ( 0.5 / (0.5 + 20) )
This comes as 0.122 V
I'm not sure why they've mentioned I leakage and does 0-state have any impact on answer.
R1 is not in the question. I couldn't find the circuit in question, anywhere in the book about opamp. So I searched for input resistance of opamp and the link came up.
We can like assume R1 to be wire resistance and then consider it is equal to negligible i.e 0.
The original question is the one...
The resistance between input signal source and ground would be same as resistance between signal source and input of opamp, which is zero here. Now since the non-inverting terminal is grounded, then the inverting terminal is also grounded, so the entire input signal shorts to the ground?? But...
Ok. Thanks. Just for knowledge: if current is going into the output of the opamp, then where does it go from there? Like current needs a closed path.
So if current enters opamp from output, where does it come out from?
Or if current is coming out from output of opamp, how does it enter the opamp?